1. Field of the Invention
The present invention relates to a semiconductor device equipped with a pull-down circuit for fixing a predetermined terminal of a predetermined circuit to low when power is turned on and when a power supply voltage decreases.
2. Description of the Related Art
In a semiconductor device, in some cases, a pull-down circuit is provided to an internal node which needs to be fixed to low so as to prevent malfunction thereof when power is turned on and when a power supply voltage decreases, whereby the pull-down circuit fixes the internal node to low when the power is turned on and when the power supply voltage decreases.
A semiconductor device equipped with a conventional pull-down circuit is described. FIG. 2 is a schematic circuit diagram of a semiconductor device equipped with a conventional pull-down circuit.
A pull-down circuit 40 includes a depletion type NMOS transistor 41. The pull-down circuit 40 includes a terminal 42. In the depletion type NMOS transistor 41, a gate and a source thereof are connected to a ground terminal, and a drain thereof is connected to a pull-down node 31 through the terminal 42. Moreover, in order to prevent that a voltage of the pull-down node 31 increases precipitously to momentarily become high due to power-on and decrease in power supply voltage of a latch circuit 20, there is also generally provided a capacitor (not shown) between the pull-down node 31 and the ground terminal.
Here, the pull-down circuit 40 fixes the pull-down node 31 (terminal 24 of the latch circuit 20) to low when the power is turned on and when the power supply voltage decreases. Further, the depletion type NMOS transistor 41 has a characteristic that the gate and the source thereof are connected to the ground terminal to make a drain current a constant current, and is used also as a constant-current circuit. Depending on variation and a temperature characteristic of the constant current, the circuit design is made so that a threshold voltage of the depletion type NMOS transistor 41 is set to about −0.5 V to −0.4 V (for example, see JP 2003-332892 A).
Further, in place of the depletion type NMOS transistor 41, a high-resistance element (not shown) is provided as the pull-down circuit 40 between the pull-down node 31 (terminal 42) and the ground terminal in some cases.
However, when it is structured to reduce a consumption current of the depletion type NMOS transistor 41, a resistance value of an on-resistance of the depletion type NMOS transistor 41 increases, thereby increasing an L length of the depletion type NMOS transistor 41. As a result, an area of the pull-down circuit 40 including the depletion type NMOS transistor 41 increases, and correspondingly, an area of the semiconductor device increases as well.
Alternatively, when the high-resistance element is used in place of the depletion type NMOS transistor 41 so as to reduce the consumption current of the high-resistance element, a resistance value of the high-resistance element becomes larger, thereby increasing a length of the high-resistance element. Accordingly, the area of the pull-down circuit 40 including the high-resistance element increases, and correspondingly, the area of the semiconductor device increases as well.